The present invention relates generally to integrated circuit (IC) designs, and more particularly to a metal oxide semiconductor (MOS) device with a metal gate and a cap layer.
Conventionally, the gate conductor of a semiconductor device, such as a complementary metal-oxide-semiconductor (CMOS) transistor, is made of polycrystalline silicon doped with either N-type or P-type impurities. While such doped impurities reduce the resistance of the poly-silicon gate conductor, they have undesired electrical characteristics. The doped poly-silicon gate conductor would induce an undesired depletion region thereunder in a substrate. As the size of a semiconductor device keeps shrinking, this undesired depletion region may significantly hinder the improvement of its performance. Thus, it is desirable to replace the conventional poly-silicon gate conductor with other materials that do not require impurity doping, in order to avoid this depletion problem.
Another challenge facing the poly-silicon gate is its low quality electrical interface with a metal contact. To meet this challenge, a silicide layer is formed atop the poly-silicon gate conductor as its interface with the metal contact to reduce resistance thereacross. The silicide layer can be formed by a series of process steps, called self-aligned silicide (salicide) technology, that eliminates a photolithography step, and provides a near perfect alignment for the silicide layer and the poly-silicon gate conductor. This is a significant advantage because, otherwise, the photolithography step will impose a dimension limit on designs of semiconductor device, due to its pattern resolution. Needless to say, the photolithography step costs extra overhead.
Given the superiority of the self-aligned process, it is also desirable to form a self-aligned contact atop a source/drain region. However, the salicide technology for the poly-silicon gate conductor is often not compatible with the process steps for forming the self-aligned contact. When forming the self-aligned contact, a metal layer is deposited over the source/drain regions, thermally treated, and then etched back. In order to avoid an undesired electrical connection between the gate conductor and the source/drain regions through the self-aligned contact, a cap layer is usually formed atop the gate conductor as a protection layer. Because of this cap layer, the salicide layer and the self-aligned contact cannot be formed in the same process steps.
What is needed is MOS device with a gate structure of a non-ploy-silicon material, which eliminates the need of a salicide layer, such that the self-aligned contact may be implemented in a simplified fabrication process.